ex_4_2_decoder.vhd

This is the course for VHDL programming

library IEEE;
use IEEE.std_logic_1164.all;
entity DECODE is
port(ADR : in  STD_LOGIC_VECTOR(2 downto 0);
     Y: out STD_LOGIC_VECTOR (7 downto 0));
end DECODE;
Architecture DF of DECODE is
Begin
	
	Y<=	
	   "00000001" when ADR="000" else
		"00000010" when ADR="001" else
		"00000100" when ADR="010" else
		"00001000" when ADR="011" else
		"00010000" when ADR="100" else
		"00100000" when ADR="101" else
		"01000000" when ADR="110" else
		"10000000" when ADR="111" else
		"XXXXXXXX" ;
End DF;