ex_p4_11_look_ahead_add.vhd

来自「This is the course for VHDL programming」· VHDL 代码 · 共 27 行

-- 4 bit Look ahead adder
entity LA_ADDER4 is
	port (A,B: in BIT_VECTOR(3 downto 0);Cin:in BIT;
		S:out BIT_VECTOR(3 downto 0);Cout:out BIT);
end LA_ADDER4;
architecture DF of LA_ADDER4 is
	signal G0,G1,G2,G3,C1,C2,C3,P0,P1,P2,P3: BIT;
begin
	G0<=A(0) and B(0);
	G1<=A(1) and B(1);
	G2<=A(2) and B(2);
	G3<=A(3) and B(3);
	P0<=A(0) xor B(0);
	P1<=A(1) xor B(1);
	P2<=A(2) xor B(2);
	P3<=A(3) xor B(3);
	C1<=G0 or (P0 and Cin);
	C2<=G1 or (G0 and P1) or (P0 and P1 and Cin)  ;
	C3<=G2 or (G1 and P2)or (G0 and P1 and P2) or (P0 and P1 and P2 and Cin)  ;
	Cout<= G3 or (G2 and P3) or (G1 and P1 and P2)
		or (G0 and P1 and P2 and P3) or (P0 and P1 and P2 and P3 and Cin)  ;
	S(0)<= P0 xor Cin;
	S(1)<= P1 xor C1;
	S(2)<= P2 xor C2;
	S(3)<= P3 xor C3;
end DF;