ex_p4_21_sync_counter.vhd

This is the course for VHDL programming

--COUNTER 74163
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity CNT163 is
	port (P:in std_logic_vector(3 downto 0);
		CLK,EN_P,EN_T,RESET_BAR,LOAD_BAR:in std_logic;
		Q: out std_logic_vector(3 downto 0);
		TC:out std_logic);
end CNT163 ;

architecture BEH of CNT163  is
	signal INT_COUNT:std_logic_vector(3 downto 0);
begin
	process(clk,reset_bar,en_p,en_t,load_bar)
	begin
		if CLK'event and CLK='1' then
			if RESET_BAR='0' then INT_COUNT<= "0000";
			elsif LOAD_BAR='0' then INT_COUNT<= P;
			elsif EN_P='1' and EN_T='1' then 
INT_COUNT<= INT_COUNT+1 ;
			end if;
		end if; 
	end process;
	TC <= '1' when INT_COUNT= "1111" else '0';	
	Q <= INT_COUNT;
end BEH;