ex_p4_16_neg_jkff.vhd

来自「This is the course for VHDL programming」· VHDL 代码 · 共 19 行

entity N_JKFF is
	port (J,K,CLK,RESET_BAR:in BIT;Q:out BIT);
end N_JKFF ;
architecture BEH of N_JKFF  is
	signal INT_Q:BIT;-- INT_Q= intermediate Q
begin
	process(J,K,CLK,RESET_BAR,INT_Q)
	begin
		if RESET_BAR = '0' then INT_Q <='0';
		elsif CLK'event and CLK='1'then
			if    J='0' and K='1' then INT_Q<='0';
			elsif J='1' and K='0' then INT_Q<='1';
			elsif J='1' and K='1' then INT_Q<=not INT_Q;
			end if;
		end if;
   end process;
	Q<=INT_Q;
end BEH;