ex_p4_14_unishift.vhd

来自「This is the course for VHDL programming」· VHDL 代码 · 共 23 行

entity unishift is
	port(P_IN:in  bit_vector(7 downto 0);--Input
		  P_OUT:out bit_vector(7 downto 0);--Output
        MODE:in  bit_vector(1 downto 0);
		  RST,CLK,LEFT_IN,RIGHT_IN:in bit);
end unishift;
architecture DF of unishift is
	signal REG:bit_vector(7 downto 0);
begin
    process(CLK,RST)
    begin
        if RST = '1' then REG <= "00000000";
        elsif CLK = '1' and CLK'event then
            case MODE is
                when "00" => REG <= REG;
                when "01" => REG <= REG(6 downto 0) & RIGHT_IN;
                when "10" => REG <= LEFT_IN & REG(7 downto 1);   
                when "11" => REG <= P_IN;
           end case;
        end if;
    end process;
    P_OUT <= REG;
end DF;