ex_4_3_prio.vhd

This is the course for VHDL programming

library ieee;
use ieee.std_logic_1164.all;
entity PRI_ENC is
	port(I:in std_logic_vector(3 downto 0);
		   P:out std_logic_vector(1 downto 0);
		   A:out std_logic);
end PRI_ENC;
architecture DF_SEL of PRI_ENC is
begin
	A <= I(0) or I(1) or I(2) or I(3);
	with I select
		P <= "11" when "1000"|"1001"|"1010"|"1011"|
                     "1100"|"1101"|"1110"|"1111",
			 "10" when "0100"|"0101"|"0110"|"0111",
			 "01" when "0010"|"0011",
			 "00" when "0001"|"0000",
			 "XX" when others;
end DF_SEL;