ex_p4_23_cond_examplw.vhd

来自「This is the course for VHDL programming」· VHDL 代码 · 共 15 行

entity try is
end try;

architecture DATAFLOW of try is
signal a, b: bit;
signal c: bit_vector(1 downto 0);
begin
		a <= '1' after 10 ns,'0' after 30 ns;
		b <= '1' after 20 ns,'0' after 40 ns, '1' after 50 ns;
		c <= 	"01" when (a = '1')else
			"10" when (a and b)= '1' else
			"11" when (b = '0') else
			"00";
end DATAFLOW;