ex_p4_28_normalizer.vhd

This is the course for VHDL programming

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-- Floating point normalizer
entity NORM is
	port (A: in std_logic_VECTOR(31 downto 0);
			N:out std_logic_VECTOR(31 downto 0));
end NORM;
architecture DF of NORM is
	alias sign:std_logic is A(31);
	alias exponent:std_logic_vector(7 downto 0) is 
	               A(30 downto 23);
	alias mantissa:std_logic_vector(22 downto 0) is 
	               A(22 downto 0);
	signal leading_zeros: std_logic_vector(4 downto 0);
	signal exp2:std_logic_vector(7 downto 0);
   signal mantissa2:std_logic_vector(22 downto 0);
begin
    process(mantissa)
        variable LZ:std_logic_vector(4 downto 0);
    begin
        LZ := "00000";
        for i in 0 to 22 loop
           exit when (mantissa(22-i)) = '1';
           LZ := LZ + 1;
       end loop;
       leading_zeros <= LZ;
   end process;
   exp2 <= exponent - leading_zeros;
   mantissa2 <= To_stdlogicvector(
            To_bitvector(mantissa) sll 
            conv_integer(leading_zeros));
   N <= sign & exp2 & mantissa2;
end DF;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity NORM_TB is end  NORM_TB;
architecture BEH of NORM_TB is
   signal mantissa:std_logic_vector(22 downto 0)
                  := "011" & X"00000"; 
   signal exp:std_logic_vector(7 downto 0)
                  := "10000111";
   signal sign:std_logic:='0';
   signal A,N:std_logic_vector(31 downto 0);
begin
   exp <= "10000110" after 100 ns,
          "10000101" after 200 ns,
          "10000100" after 300 ns;
    mantissa <= "000" & X"C0000" after 100 ns;
    A <= sign & exp & mantissa;
    N1:entity work.NORM
       port map(A,N);
end BEH;