ex_p4_19_alu.vhd

This is the course for VHDL programming

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity ALU8 is
	PORT (
	   A,B: in std_logic_vector(7 downto 0);
		RESULT: out std_logic_vector(7 downto 0);
		OP_CODE: in std_logic_vector(1 downto 0)
		);

end ALU8;
architecture DF of ALU8 is
    -- Function to truncate multiplier result 
    -- to 8 bits
    function mult(A,B: std_logic_vector)
       return std_logic_vector is
       variable C : std_logic_vector(15 downto 0);
    begin
        C := A*B;
        return C(7 downto 0);
    end mult;
    -- Function to overload "/" operator 
    -- for std_logic data type
    function "/"(A,B: std_logic_vector)
       return std_logic_vector is
       variable C : integer;
    begin
        C := conv_integer(A)/ conv_integer(B);
        return conv_std_logic_vector(C,8);
    end "/";
begin
	with OP_CODE select
	RESULT <= A+B        when "00",
	          A-B        when "01",
	          mult(A,B)  when "10",
	          A/B        when "11",
	          "XXXXXXXX" when others;
end DF;