ex_p4_13_bcd_to_7seg.vhd

来自「This is the course for VHDL programming」· VHDL 代码 · 共 63 行

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity BCD_7SEG is
	port (BCD :in std_logic_vector(3 downto 0);
	      SEVEN_SEG:out std_logic_vector(6 downto 0));
end BCD_7SEG ;
-- MSB of SEVEN_SEG is segment G of LED
-- LSB of SEVEN_SEG is segment A of LED
architecture COND of BCD_7SEG  is
begin
    SEVEN_SEG<= "0111111" when BCD="0000" else
                "0000110" when BCD="0001" else
                "1011011" when BCD="0010" else
                "1001111" when BCD="0011" else
                "1100110" when BCD="0100" else
                "1101101" when BCD="0101" else
                "1111101" when BCD="0110" else
                "0000111" when BCD="0111" else
                "1111111" when BCD="1000" else
                "1101111" ;
end COND;
architecture SEL of BCD_7SEG  is
begin
    with BCD select
    SEVEN_SEG<= "0111111" when "0000" ,
                "0000110" when "0001" ,
                "1011011" when "0010" ,
                "1001111" when "0011" ,
                "1100110" when "0100" ,
                "1101101" when "0101" ,
                "1111101" when "0110" ,
                "0000111" when "0111" ,
                "1111111" when "1000" ,
                "1101111" when others;
end SEL;
architecture IF_STMT of BCD_7SEG  is
begin
    process(BCD)
    begin
       if      BCD="0000" then SEVEN_SEG <= "0111111";
       elsif BCD="0001" then SEVEN_SEG <= "0000110";
       elsif BCD="0010" then SEVEN_SEG <= "1011011";
       elsif BCD="0011" then SEVEN_SEG <= "1001111"; 
       elsif BCD="0100" then SEVEN_SEG <= "1100110"; 
       elsif BCD="0101" then SEVEN_SEG <= "1101101"; 
       elsif BCD="0110" then SEVEN_SEG <= "1111101"; 
       elsif BCD="0111" then SEVEN_SEG <= "0000111"; 
       elsif BCD="1000" then SEVEN_SEG <= "1111111"; 
       else                  SEVEN_SEG <= "1101111";
   end if;
   end process; 
end IF_STMT;
architecture LUT of BCD_7SEG  is
   type ROM_ARRAY is array(0 to 9) of 
	std_logic_vector(6 downto 0);
constant ROM:ROM_ARRAY:=
	("0111111","0000110","1011011","1001111","1100110",
	 "1101101","1111101","0000111","1111111","1101111"
	);
begin
    SEVEN_SEG <= ROM(conv_integer(BCD));
end LUT;