ex_p4_20_l0_counter.vhd

来自「This is the course for VHDL programming」· VHDL 代码 · 共 25 行

--Leading zero counter
entity L0CNTR is
	PORT (N:  in bit_vector(15 downto 0);
		   NZ:out bit_vector(4  downto 0));
end L0CNTR;
architecture DF of L0CNTR is
begin
    NZ <= "00000" when N(15) = '1' else
          "00001" when N(14) = '1' else
          "00010" when N(13) = '1' else
          "00011" when N(12) = '1' else
          "00100" when N(11) = '1' else
          "00101" when N(10) = '1' else
          "00110" when N(9) = '1' else
          "00111" when N(8) = '1' else
          "01000" when N(7) = '1' else
          "01001" when N(6) = '1' else
          "01010" when N(5) = '1' else
          "01011" when N(4) = '1' else
          "01100" when N(3) = '1' else
          "01101" when N(2) = '1' else
          "01110" when N(1) = '1' else
          "01111" when N(0) = '1' else
          "10000";
end DF;