ex_4_5_tff.vhd

This is the course for VHDL programming

entity TFF is	
   port(T,CLK,RST: in BIT ;
        Q : out BIT) ;	
end TFF;
architecture DF_DELAY of TFF is
begin
	process(CLK,RST,T)
	    variable int_Q:bit;
	begin
	    if RST = '1' then int_Q := '1';
	    elsif CLK'event and CLK = '1' then
	        if T= '1' then 
	           int_Q := not int_Q after 5 ns;
	        end if;
	    end if;
	    Q <= int_Q;
	end process;
end DF_DELAY;