ex_p4_8_e3_to_bcd.vhd

This is the course for VHDL programming

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity CONV is
	port (E3:in std_logic_vector(3 downto 0);
			BCD :out std_logic_vector(3 downto 0));
end CONV ;

architecture DATAFLOW of CONV  is
type ROM_ARRAY is array(3 to 12) of 
	std_logic_vector(3 downto 0);
constant ROM:ROM_ARRAY:=
	("0000","0001","0010","0011","0100",
	 "0101","0110","0111","1000","1001");
begin
	BCD<=ROM(conv_integer(E3));
end DATAFLOW;