ex_p4_7_sel_ass.vhd

来自「This is the course for VHDL programming」· VHDL 代码 · 共 17 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity TEST4_6 is end TEST4_6;
architecture DF of TEST4_6 is
    signal J,K,L:integer;
begin
    with J select
    K <= 0 when integer'low to -1,
         J+1 when 0 to 2,
         100 when 50|75,
         500 when others;
    L <= 0 when J <0 else
         J+1 when (J>=0) and (J<=2) else
         100 when (J=50) or (J=75) else
         500;     
end DF;