ex_p4_12_data_splitter.vhd

This is the course for VHDL programming

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity data_splitter is 
   port(DI: in std_logic_vector(7 downto 0);
       DO0,DO1,DO2,DO3: out std_logic_vector(7 downto 0);
       CLK,RST : in std_logic);
end data_splitter;
architecture DF of data_splitter is
    signal COUNT:std_logic_vector(1 downto 0);
begin
    process(CLK,RST)
    begin
        if RST = '1' then COUNT <= "00";
        elsif CLK'event and CLK = '1' then
           COUNT <= COUNT + 1;
           case COUNT is
               when "00"   => DO0 <= DI;
               when "01"   => DO1 <= DI;
               when "10"   => DO2 <= DI;
               when others => DO3 <= DI;  
          end case; 
       end if;
   end process;
end DF;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity splitter_tb is end splitter_tb;
architecture DF of splitter_tb is
    signal DI,DO0,DO1,DO2,DO3:std_logic_vector(7 downto 0);
    signal CLK,RST : std_logic:= '1';
begin
    split:entity work.data_splitter 
       port map(DI,DO0,DO1,DO2,DO3,CLK,RST);
    RST <= '0' after 40 ns;
    process
    begin
        DI <= "00000000";
        for i in 0 to 16 loop
           wait for 50 ns;
           clk <= '1';
           wait for 50 ns;
           clk <= '0';
           DI <= DI + 1;
       end loop;
   end process;
end DF;