ex_p5_25_mult4x4.vhd

This is the course for VHDL programming

entity COMBMULT4X4 is
   port  (X,Y: in BIT_VECTOR(3 downto 0); 
          Z: out BIT_VECTOR(7 downto 0)); 
end COMBMULT4X4;

architecture STRUCT of COMBMULT4X4 is
	type PRODARRAY is array(0 to 3,0 to 3)of BIT;
	signal XY:PRODARRAY;
	signal C00,C01,C02,C10,C11,C12,C20,C21,C22,C30,C31:BIT;
	signal S01,S02,S11,S12,S21,S22:BIT;
	component FA 
	   port(x,y,ci:in BIT;sum,co:out BIT);
	end component;
	for all:FA use entity work.FA(struct);
begin
	GEN1:for i in 0 to 3 generate
		GEN2:for j in 0 to 3 generate
			GEN3:XY(i,j) <= X(i) and Y(j);
		end generate;
	end generate;
	FA00:FA port map(XY(1,0),'0' ,XY(0,1),Z(1),C00);
	FA01:FA port map(XY(2,0),'0' ,XY(1,1),S01 ,C01);
	FA02:FA port map(XY(3,0),'0' ,XY(2,1),S02 ,C02);
	FA10:FA port map(S01    ,C00 ,XY(0,2),Z(2),C10);
	FA11:FA port map(S02    ,C01 ,XY(1,2),S11 ,C11);
	FA12:FA port map(XY(3,1),C02 ,XY(2,2),S12 ,C12);
	FA20:FA port map(S11    ,C10 ,XY(0,3),Z(3),C20);
	FA21:FA port map(s12    ,C11 ,XY(1,3),S21 ,C21);
	FA22:FA port map(XY(3,2),C12 ,XY(2,3),S22 ,C22);
	FA30:FA port map(S21    ,C20 ,'0'    ,Z(4),C30);
	FA31:FA port map(S22    ,C21 ,C30    ,Z(5),C31);
	FA32:FA port map(XY(3,3),C22 ,C31    ,Z(6),Z(7));
	Z(0) <= XY(0,0);
end STRUCT;