ex_p5_7_mult_config.vhd

This is the course for VHDL programming

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
package conv_func is
   function to_bitvect(slv:STD_LOGIC_VECTOR) return BIT_VECTOR;
end conv_func;
package body conv_func is
   function to_bitvect(slv:STD_LOGIC_VECTOR) return BIT_VECTOR is
   begin
       return to_bitvector(slv);
   end to_bitvect;
end conv_func;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity MULT8 is
			port(	A,B: in BIT_VECTOR(7 downto 0); 
               C: out BIT_VECTOR(15 downto 0));
		End MULT8;
architecture FAST of MULT8 is
begin
    C <= to_bitvector(to_stdlogicvector(A)
                      *to_stdlogicvector(B));
end FAST;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.conv_func.all;
entity DSP is  
   port( R: out STD_LOGIC_VECTOR(15 downto 0);
			P,Q :in STD_LOGIC_VECTOR(7 downto 0));
end DSP;
architecture STRUCT of DSP is
   component MULTIPLIER
	   port(	Z: out STD_LOGIC_VECTOR(15 downto 0);
			X,Y :in STD_LOGIC_VECTOR(7 downto 0));
	end component;
begin
    M:MULTIPLIER port map(R,P,Q);
end STRUCT;
configuration DSP_CONFIG of DSP is
    for STRUCT
       for M:MULTIPLIER use entity work.MULT8
          port map(A => to_bitvect(X),
                   B => to_bitvect(Y),
                   to_stdlogicvector(C) => R);
       end for;
   end for;
end DSP_CONFIG;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DSP_CONFIG;
entity DSP_TB is  end DSP_TB;
architecture STRUCT of DSP_TB is
   component DSP
	   port(	R: out STD_LOGIC_VECTOR(15 downto 0);
			P,Q :in STD_LOGIC_VECTOR(7 downto 0));
	end component;
	signal D,E : STD_LOGIC_VECTOR(7 downto 0);
   signal F  : STD_LOGIC_VECTOR(15 downto 0);
begin
    DD:DSP port map(F,D,E);
end STRUCT;