ex_p5_28_bcd_adder.vhd

来自「This is the course for VHDL programming」· VHDL 代码 · 共 25 行

entity BCD_A is
	port(x,y:in BIT_VECTOR(3 downto 0);
	     ci:in BIT;
	     sum: out BIT_VECTOR(3 downto 0);
	     co:out BIT);
end BCD_A;
architecture struct of BCD_A is
   signal s1,s2: BIT_VECTOR(3 downto 0);
   signal c,cint: BIT;
   component NA is
	port(a,b:in BIT_vector(3 downto 0);
		  cin :in BIT;
		  s   :out BIT_vector(3 downto 0);
		  cout:out BIT
	     );
   end component;
begin
   A1:NA port map(x,y,ci,s1,c);
   cint <= '1' when (c = '1') or 
      (s1(3)='1' and (s1(2)='1' or s1(1)='1'))else
       '0';
   co <= cint;
   s2 <= ('0',cint,cint,'0');
   A2:NA port map(s1,s2,'0',sum,open);
end struct;