ex_5_6_ram_8_chips.vhd

This is the course for VHDL programming

--RAM1K-------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity RAM1K is
	port (ADR:in std_logic_vector(9 downto 0):=(OTHERS=>'0');
		CS_BAR,OE_BAR,WR_BAR:in std_logic;
		D:inout std_logic_vector(7 downto 0));
	constant acc_time:time:=50 ns;
end RAM1K ;

architecture DATAFLOW of RAM1K  is
type RAM_ARRAY is array(0 to 1023) of std_logic_vector(7 downto 0);
signal RAM:RAM_ARRAY;
begin
	D<=RAM(conv_integer(ADR)) after acc_time when CS_BAR='0' and OE_BAR='0' else
	   (others=>'Z');	
	RAM(conv_integer(ADR)) <= D when CS_BAR='0' and WR_BAR='0' else
					RAM(conv_integer(ADR)) ;
end DATAFLOW;
--DECODER-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity DECODER is
port(ADR : in  STD_LOGIC_VECTOR(2 downto 0):="000";
	Y: out STD_LOGIC_VECTOR (7 downto 0));

End DECODER;
Architecture DF of DECODER is
Begin
	With ADR select
	Y<=	"11111110" when "000",
		"11111101" when "001",
		"11111011" when "010",
		"11110111" when "011",
		"11101111" when "100",
		"11011111" when "101",
		"10111111" when "110",
		"01111111" when "111",
		"XXXXXXXX" when others;
End DF;
--RAM8 --------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.all;
entity ram8 is
	port(MEMR_BAR,MEMW_BAR : in std_logic;
		ADDR : in std_logic_vector(12 downto 0):=(OTHERS=>'0');
		DATA : inout std_logic_vector (7 downto 0));
end ram8;


architecture struct of ram8 is
	component RAM1K
		port(ADR:in std_logic_vector(9 downto 0):=(OTHERS=>'0');
			CS_BAR,OE_BAR,WR_BAR:in std_logic;
			D:inout std_logic_vector(7 downto 0));
	end component;
      COMPONENT DECODER
		port(adr : in std_logic_vector(2 downto 0);
		y : out std_logic_vector(7 downto 0));
	end COMPONENT;

SIGNAL CS: STD_LOGIC_VECTOR (7 DOWNTO 0);
Begin
	DECODER1 : DECODER PORT MAP (addr(12 downto 10), CS);
	RAM:for i in 0 to 7 generate
GENRAM: RAM1K port map(ADDR(9 downto 0), CS(i), MEMR_BAR,MEMW_BAR, DATA);
	end generate;
end struct;