ex_p5_22_n_squared_parity_gen.vhd

This is the course for VHDL programming

entity PARITY_N2 is
	generic(N:integer:=4);
	port (D:in BIT_VECTOR(0 to N*N-1);
	      P:out BIT );
end PARITY_N2 ;

architecture STRUCT of PARITY_N2 is
   component PARITY
      generic(N:integer:=8);
	   port (DATA:in BIT_VECTOR(0 to N-1);
	         P:out BIT );
   end component ;
   for all:PARITY use entity work.PARITY;
   signal PV:BIT_VECTOR(0 to N-1);
begin
    G:for i in 0 to N-1 generate
    P:PARITY generic map(N) 
             port map(D(i*N  to (i+1)*N -1),
                      PV(i));
    end generate;
    PP:PARITY generic map(N) 
             port map(PV,P);
end STRUCT;