ex_p5_26_fsm_pack.vhd

This is the course for VHDL programming

package fsm_pack is
   type STATES is(RESET,GOT1,GOT10,GOT101,GOT1011);
	type TWO_D_ARRAY is array(STATES,BIT) of STATES;
	type ONE_D_ARRAY is array(STATES) of BIT;
	constant NS_TBL: TWO_D_ARRAY:=
		((RESET, GOT1),
		  (GOT10, GOT1),
		  (RESET, GOT101),
		  (GOT10, GOT1011),
		  (RESET, GOT1));
	constant OUT_TBL:ONE_D_ARRAY:= ('0','0','0','0','1');
end fsm_pack;

use work.fsm_pack.all;
entity FSM1011 is
   generic(NS_TBL1 : TWO_D_ARRAY := NS_TBL;
           OUT_TBL1: ONE_D_ARRAY := OUT_TBL);
	port(RST,X,CLK :in BIT; Z: out BIT);
end FSM1011;

architecture PACK of FSM1011 is
	signal STATE,NEXT_STATE : STATES;
begin
   process(CLK,RST,X)
	begin
	   if(RST='1')then STATE <= RESET;
	   elsif(CLK'event and CLK='1') then
		   STATE<= NS_TBL1(STATE,X);
	   end if;
   end process;
   Z <= OUT_TBL1(STATE);
end PACK;
entity FSM1011_TB is end FSM1011_TB;
architecture BEH of FSM1011_TB is
	signal RST,X,CLK,Z : BIT;
begin
   F:entity work.FSM1011(PACK)
      port map(RST,X,CLK,Z);
   process
       variable clk_count:integer:=0;
    begin
       RST <= '1';wait for 50 ns;
       RST <= '0';
       for i in 0 to 12 loop
          wait for 50 ns;
          clk<= not clk;
       end loop;
       wait;
   end process;
   X <= '1' after 50 ns,'0' after 150 ns,
        '1' after 250 ns;
end BEH;