ex_p5_8_mult_config_stmt.vhd

来自「This is the course for VHDL programming」· VHDL 代码 · 共 20 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.conv_func.all;
entity DSP is  
   port( R: out STD_LOGIC_VECTOR(15 downto 0);
			P,Q :in STD_LOGIC_VECTOR(7 downto 0));
end DSP;
architecture STRUCT of DSP is
   component MULTIPLIER
	   port(	Z: out STD_LOGIC_VECTOR(15 downto 0);
			X,Y :in STD_LOGIC_VECTOR(7 downto 0));
	end component;
	for M:MULTIPLIER use entity work.MULT8
          port map(A => to_bitvect(X),
                   B => to_bitvect(Y),
                   to_stdlogicvector(C) => R);
begin
    M:MULTIPLIER port map(R,P,Q);
end STRUCT;