ex_5_2_adder.vhd

This is the course for VHDL programming

--  BASIC GATES
entity and2 is	port(i1,i2: in BIT ;o : out BIT) ;	end and2;
architecture DF of and2 is
begin
	o<= i1 and i2 after 2 ns;
end DF;
entity xor2 is	port(i1,i2: in BIT ;o : out BIT) ;	end xor2;
architecture DF of xor2 is
begin
	o<= i1 xor i2 after 5 ns;
end DF;
entity OR2 is
	port(i1,i2:in BIT;o:out BIT);
end OR2;
architecture dataflow of OR2 is
begin
	o<= i1 or i2 after 3 ns;
end dataflow;
-- HALF ADDER - DATAFLOW
entity HA is	port(a, b :in BIT; s, c: out BIT);	end HA;
architecture dataflow of HA is
begin
	s<= a xor b after 5 ns;
	c<= a and b after 10 ns;
end dataflow;
-- HALF ADDER - STRUCTURAL
architecture arch_struct of HA is
component and2 port (i1,i2: in BIT ;o : out BIT); end component;
component xor2 port (i1,i2: in BIT ; o: out BIT); end component;
begin
	A1: and2 port map (a, b, c);
	X1: xor2 port map (a, b, s);
end arch_struct;
--STRUCTURAL DESCRIPTION OF FULL ADDER
entity FA is
	port(x,y,ci:in BIT;sum,co:out BIT);
end FA;
architecture struct of FA is
component HA  port(a,b:in BIT;s,c:out BIT);end component;
component OR2 port(i1,i2:in BIT;o:out BIT);end component;
signal s1,c1,c2: BIT;
begin
	HA1:HA  port map(x ,y ,s1  ,c1);
	HA2:HA  port map(s1,ci,sum ,c2);
	ORG:OR2 port map(c1,c2,co);
end struct;
configuration MYCONFIG of FA is
	    For struct
		For HA1: HA use entity WORK.HA (dataflow); end for;
		For HA2: HA use entity WORK.HA (dataflow)
			port map (a => a, b => b, s => s, c => c);
end for;
		For ORG: OR2 use entity WORK.OR2 (dataflow); end for;
	    End for;
end MYCONFIG;
Configuration NESTCONFIG of FA is
	For struct
		For HA1: HA use entity WORK.HA (dataflow); end for;
		For HA2: HA use entity WORK.HA (arch_struct);
			For arch_struct
				For A1: and2 use entity WORK.and2(DF);End for;
				For X1: xor2 use entity WORK.xor2(DF);End for;
			End for;
      end for;
		For ORG: OR2 use entity WORK.OR2(dataflow); end for;
	End for;
End NESTCONFIG;
entity BA is
	port(a,b:in BIT_vector(7 downto 0);
		cin :in BIT;
		s   :out BIT_vector(7 downto 0);
		cout:out BIT
	     );
end BA;
architecture struct_generate of BA is
	component FA 
		port(x,y,ci:in BIT;sum,co:out BIT);
	end component;
	signal c:BIT_vector(6 downto 0);
for all:FA use configuration work.NESTCONFIG;
begin
	FA0  :FA port map(a(0),b(0),cin,s(0),c(0));
	FAmid:for i in 1 to 6 generate
			FAm:FA port map(a(i),b(i),c(i-1),s(i),c(i));
			end generate;
	FA7  :FA port map(a(7),b(7),c(6),s(7),cout);
end struct_generate;
architecture if_generate of BA is
	component FA 
		port(x,y,ci:in BIT;sum,co:out BIT);
	end component;
	signal c:BIT_vector(6 downto 0);
for all:FA use configuration work.NESTCONFIG;
begin
	FA_GEN: for i in 0 to 7 generate 
        G1:If i = 0  	     generate FA0:FA port map(a(i),b(i), cin,s (i),c(i)); end generate;
        G2:If i >0 and i<7 generate FAm:FA port map(a(i),b(i),c(i-1),s(i),c(i)); end generate;
        G3:If i =7 	       generate FA7:FA port map(a(i),b(i),c(i),s(i),cout); end generate;
   end generate FA_GEN;
end if_generate;
architecture struct_generate2 of BA is  -- Single generate, assignments for end signals
	component FA 
		port(x,y,ci:in BIT;sum,co:out BIT);
	end component;
	type b_vector is array(7 downto -1) of bit;
	signal c:b_vector;
begin
	c(-1) <=  cin;
	FAmid:for i in 0 to 7 generate
			FAm:FA port map(a(i),b(i),c(i-1),s(i),c(i));
			end generate;
	cout <= c(7);
end struct_generate2;