ex_p5_17_dword_adder.vhd

来自「This is the course for VHDL programming」· VHDL 代码 · 共 34 行

--Double word adder
entity DWA is
	port(a,b:in  BIT_vector(31 downto 0);
		  cin:in  BIT;
		  s  :out BIT_vector(31 downto 0);
		  cout:out BIT
	     );
end DWA;
architecture struct_generate of DWA is
	component BA 
		port( a,b:in BIT_vector(7 downto 0);
		      cin :in BIT;
		      s   :out BIT_vector(7 downto 0);
		      cout:out BIT
	        );
	end component;
	for all:BA use entity work.BA;
	signal c:BIT_vector(2 downto 0);
begin
	BA0  :BA port map
	      (a(7 downto 0),b(7 downto 0),
	       cin,s(7 downto 0),c(0));
	BAmid:for i in 1 to 2 generate
			BAm:BA port map
			   (a(8*i+7 downto 8*i),
			    b(8*i+7 downto 8*i),
	          c(i-1),
	          s(8*i+7 downto 8*i),c(i));
			end generate;
	BA7  :BA port map
	           (a(31 downto 24),b(31 downto 24),
	            c(2),s(31 downto 24),cout);
end struct_generate;