ex_p5_13_complementer.vhd

This is the course for VHDL programming

entity xor2 is	
   port(i1,i2: in BIT ;o : out BIT) ;	
end xor2;
architecture DF of xor2 is
begin
	o<= i1 xor i2 after 5 ns;
end DF;
entity complementer is	
   port( A: in BIT_VECTOR(7 downto 0);  
         complement: in BIT ;
         B: out BIT_VECTOR(7 downto 0)) ;	
end complementer;
architecture struct of complementer is
    component xor2 
       port (i1,i2: in BIT ; o: out BIT);
    end component;
begin
	XOR_GEN:for i in 0 to 7 generate
	   X:xor2 port map(A(i),complement,B(i));
	end generate;
end STRUCT;