ex_p5_30_complementer.vhd

This is the course for VHDL programming

entity comple_cell is	
   port( A,ci: in BIT;  
         B,co: out BIT) ;	
end comple_cell;
architecture DF of comple_cell is
begin
    co <= A or ci after 5 ns;
    B <= A xor ci after 8 ns;
end DF;
entity comple_new is
   generic(N:integer:=8);
   port( A: in BIT_VECTOR(N-1 downto 0);  
         B: out BIT_VECTOR(N-1 downto 0)) ;	
end comple_new;
architecture struct of comple_new is
    signal c:BIT_VECTOR(N downto 0);
begin
    c(0) <= '0';
    G:for i in N-1 downto 0 generate
    CM:entity work.comple_cell
       port map(A(i),c(i),B(i),c(i+1));
    end generate;
end struct;