ex_p5_18_tff_cascade.vhd

This is the course for VHDL programming

entity TFF is	
   port(T,CLK,RST: in BIT ;
        Q : out BIT) ;	
end TFF;
architecture DF of TFF is
begin
	process(CLK,RST,T)
	    variable int_Q:bit;
	begin
	    if RST = '1' then int_Q := '1';
	    elsif CLK'event and CLK = '1' then
	        if T= '1' then int_Q := not int_Q;
	        end if;
	    end if;
	    Q <= int_Q;
	end process;
end DF;
entity TFF_CELL is	
   port(ENB_IN,CLK,RST: in BIT ;
        Q_OUT : out BIT;
        ENB_OUT : out BIT) ;	
end TFF_CELL;
architecture DF of TFF_CELL is
    signal TFF_Q:bit;
begin
   T:entity work.TFF 
         port map(ENB_IN,CLK,RST,TFF_Q);
   ENB_OUT <= TFF_Q and ENB_IN;
   Q_OUT <= TFF_Q;
end DF;
entity TFF_CASCADE is	
   generic(N:integer:=8);
   port(ENB_IN,CLK,RST: in BIT ;
        COUNT:out BIT_VECTOR(N-1 downto 0);
        ENB_OUT : out BIT) ;	
end TFF_CASCADE;
architecture struct_generate of TFF_CASCADE is
    component TFF_CELL
       port(ENB_IN,CLK,RST: in BIT ;
           Q_OUT : out BIT;
           ENB_OUT : out BIT) ;	
    end component;
    --for all:TFF_CELL use work.TFF_CELL;
    signal ENB:bit_vector(N-1 downto 0);
begin
   T0  :TFF_CELL port map
	      (ENB_IN,CLK,RST,COUNT(0),ENB(0));
	Tmid:for i in 1 to N-2 generate
			Tm:TFF_CELL port map
			   (ENB(i-1),CLK,RST,COUNT(i),ENB(i));
		end generate;
	TN_1:TFF_CELL port map
	         (ENB(N-1),CLK,RST,COUNT(N-1),ENB_OUT);
end struct_generate;