ex_p5_14_add_sub.vhd

来自「This is the course for VHDL programming」· VHDL 代码 · 共 25 行

entity ADD_SUB is	
   port( A,B: in BIT_VECTOR(7 downto 0);  
         SUB,Cin: in BIT ;
         Cout: out BIT ;
         C: out BIT_VECTOR(7 downto 0)) ;	
end ADD_SUB;
architecture struct of ADD_SUB is
    component complementer 
       port( A: in BIT_VECTOR(7 downto 0);  
             complement: in BIT ;
             B: out BIT_VECTOR(7 downto 0)) ;	
    end component;
    component BA
       port(a,b:in BIT_vector(7 downto 0);
		      cin :in BIT;
		      s   :out BIT_vector(7 downto 0);
		      cout:out BIT
	         );
	 end component;
    signal B_BAR:BIT_VECTOR(7 downto 0);
begin
	CM1:complementer port map(B,SUB,B_BAR);
	BA1:BA port map(A,B_BAR,Cin,C,Cout);
end STRUCT;