ex_p5_27_look_ahead_adder.vhd

This is the course for VHDL programming

entity LA_CARRY is
	port (A,B: in BIT_VECTOR(3 downto 0);Cin:in BIT;
		   C:out BIT_VECTOR(1 to 4));
end LA_CARRY;
architecture DF of LA_CARRY is
	signal G0,G1,G2,G3,C1,C2,C3,P0,P1,P2,P3: BIT;
begin
	G0<=A(0) and B(0);
	G1<=A(1) and B(1);
	G2<=A(2) and B(2);
	G3<=A(3) and B(3);
	P0<=A(0) xor B(0);
	P1<=A(1) xor B(1);
	P2<=A(2) xor B(2);
	P3<=A(3) xor B(3);
	C(1)<=G0 or (P0 and Cin);
	C(2)<=G1 or (G0 and P1) or (P0 and P1 and Cin)  ;
	C(3)<=G2 or (G1 and P2)or (G0 and P1 and P2) or (P0 and P1 and P2 and Cin)  ;
	C(4)<= G3 or (G2 and P3) or (G1 and P1 and P2)
		or (G0 and P1 and P2 and P3) or (P0 and P1 and P2 and P3 and Cin)  ;
end DF;
entity NA is
	port(a,b:in BIT_vector(3 downto 0);
		  cin :in BIT;
		  s   :out BIT_vector(3 downto 0);
		  cout:out BIT
	     );
end NA;
architecture struct of NA is
	component FA 
		port(x,y,ci:in BIT;sum,co:out BIT);
	end component;
	component LA_CARRY is
	   port (A,B: in BIT_VECTOR(3 downto 0);
	         Cin:in BIT;
		      C:out BIT_VECTOR(1 to 4));
   end component;
	for all:FA use entity work.FA(struct);
   for all:LA_CARRY use entity work.LA_CARRY;
   signal C:BIT_VECTOR(1 to 4);
begin
	FA0  :FA port map(a(0),b(0),cin ,s(0),open);
	FA1  :FA port map(a(1),b(1),C(1),s(1),open);
	FA2  :FA port map(a(2),b(2),C(2),s(2),open);
	FA3  :FA port map(a(3),b(3),C(3),s(3),open);
	L:LA_CARRY port map(A,B,Cin,C);
	cout <= C(4);
end struct;