ex_p5_21_gen_nand.vhd

This is the course for VHDL programming

entity nand2 is
   generic(d:time:= 4 ns);	
   port(i1,i2: in BIT:='1';o : out BIT) ;	
end nand2;
architecture gen of nand2 is
begin
	o<= i1 nand i2 after d;
end gen;