ex_p5_12_parity_n.vhd

来自「This is the course for VHDL programming」· VHDL 代码 · 共 24 行

entity PARITY is
	generic(N:integer:=8);
	port (DATA:in BIT_VECTOR(0 to N-1);P:out BIT );
end PARITY ;
use work.xor2;
architecture STRUCT of PARITY is
	signal INT_P:BIT_VECTOR(1 to N-2);
	component XOR2 port (i1,i2: in BIT ; o: out BIT); end component;
begin
G0:for i in 1 to N-1 generate
		G1:if i=1 generate X_FIRST:XOR2 
port map (DATA(i),DATA(0),INT_P(i)); 
end generate;
		G2:if i>1 and i< N-1 
			generate X_MID :XOR2 
port map(DATA(i),INT_P(i-1),INT_P(i));
		end generate;
		G3:if i= N-1 generate X_LAST:XOR2 
port map(DATA(i),INT_P(i-1),P);
		end generate;
	end generate;
	
end STRUCT ;