ex_p5_7_mult8_new.vhd

This is the course for VHDL programming

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use work.conv_func.all;
entity MULT8 is
			port(	A,B: in BIT_VECTOR(7 downto 0); 
               C: out BIT_VECTOR(15 downto 0));
		End MULT8;
architecture FAST of MULT8 is
begin
    C <= to_bitvector(to_stdlogicvector(A)
                      *to_stdlogicvector(B));
end FAST;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use work.conv_func.all;
entity DSP is  
end DSP;
--use work.DSP_CONFIG;
architecture STRUCT of DSP is
   component MULTIPLIER
	   port(	Z: out STD_LOGIC_VECTOR(15 downto 0);
			X,Y :in STD_LOGIC_VECTOR(7 downto 0));
	end component;
	--for all:MULTIPLIER use entity work.mult8(FAST)
	--      port map--(A=>X,B=>Y,C=>Z);
	--          (A => to_bitvect(X),
   --           B => to_bitvect(Y),
   --           to_stdlogicvector(C) => Z);
   signal P,Q : STD_LOGIC_VECTOR(7 downto 0);
   signal R  : STD_LOGIC_VECTOR(15 downto 0);
begin
    N:MULTIPLIER port map(R,P,Q);
    --M: configuration work.DSP_CONFIG port map(R,P,Q);
    end STRUCT;