ex_3_8_overload.vhd

This is the course for VHDL programming

entity overload is end overload;
architecture beh of overload is
   Type LOGIC4 is ('0','1','Z','X');
   Type L4_TWO_DIM_ARR is 
      array(LOGIC4,LOGIC4)  of LOGIC4;
   Type L4_ONE_DIM_ARR is 
      array(LOGIC4)  of LOGIC4;
   Function "and" (a,b:LOGIC4) return LOGIC4 is
	   Constant and_table: L4_TWO_DIM_ARR:=
      (('0','0','0','0'),
       ('0','1','1','X'),
       ('0','1','1','X'),
       ('0','X','X','X'));
	begin
		return and_table(a,b);
   end "and";
   ----------   P 3.15 -----------------------
   Function "or" (a,b:LOGIC4) return LOGIC4 is
	   Constant or_table: L4_TWO_DIM_ARR:=
      (('0','1','1','X'),
       ('1','1','1','1'),
       ('1','1','1','1'),
       ('X','1','1','X'));
	begin
		return or_table(a,b);
   end "or";
   Function "not" (a:LOGIC4) return LOGIC4 is
	Constant not_table: L4_ONE_DIM_ARR:= 
	            ('1','0','0','X');
   begin
		return not_table (a);
   end "not";
   signal a,b,c,d,e:LOGIC4;
   -----------------------------------------
begin
    process
    begin
       for i in LOGIC4'('0') to LOGIC4'('X') loop
         for j in LOGIC4'('0') to LOGIC4'('X') loop
             a <= i;
             b <= j;
             c <= a and b;
             d <= not c;
             e <= a or b;
             wait for 1 ns;
         end loop;
       end loop;
       wait;
    end process;
end beh;