ex_3_9_2_mult8_tb.vhd

This is the course for VHDL programming

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity tb1 is end tb1;
architecture a of tb1 is
	component MULT8 
		port(INBUSQ,INBUSM:in std_logic_vector(0 to 7);
		OUTBUSHI, OUTBUSLO: out std_logic_vector(0 to 7);
		CLK, START, RESET: in std_logic;
		DONE :out std_logic);
	end component;
	signal X,Y:std_logic_vector(0 to 7);
	signal HI_BYTE,LO_BYTE:std_logic_vector(0 to 7);
	signal START, RESET,DONE: std_logic;
	signal CLK,over,test_done: std_logic:='0';

begin
	m:mult8 port map(X,Y,HI_BYTE,LO_BYTE,CLK, START, RESET,DONE);
	process(clk)
	begin
		if test_done/= '1' then clk <= not clk after 10 ns;end if;
		end process;
	process
		variable lout:LINE;
	--	variable gap:character:=' ';
		variable i,j,k,l:integer;
		variable pp,pm,mp,mm:integer:=0;--Accumulate no of tests
	begin
		--print heading
		write(lout,STRING'("++"),LEFT,10);write(lout,STRING'("+-"),LEFT,10);
		write(lout,STRING'("-+"),LEFT,10);write(lout,STRING'("--"),LEFT,10);
		writeline(output,lout);
		reset <='1';start <= '0';
		wait for 5 ns;
		reset <='0';
		X <="00000101";--Seed X
		Y <="11111111";--Seed Y
		for m in 1 to 1000 loop
			wait for 10 ns;
			i:=conv_integer(X);
			j:=conv_integer(Y);
			--collect functional coverage 
			if X(0)='0' then  
				if Y(0)='0' then pp:=pp+1;else pm:=pm+1;end if;
			else	if Y(0)='0' then mp:=pp+1;else mm:=pm+1;end if;
			end if;
			
			k:=i*j;			--Expected value
			start <='1';
			wait for 50 ns;
			start <= '0';
			wait until done = '1';
			l:=conv_integer(HI_BYTE & LO_BYTE);--Value computed by DUT
			--print functional coverage after every 10 loops
			if (m mod 10)= 0 then 
				write(lout,pp,LEFT,10);	write(lout,pm,LEFT,10);
				write(lout,mp,LEFT,10);	write(lout,mm,LEFT,10);
				writeline(output,lout);
			end if;
			if k /= l then
				write(lout,STRING'("Device failure"));
				write(lout,i,LEFT,10);	write(lout,j,LEFT,10);
				write(lout,k,LEFT,10);	write(lout,l,LEFT,10);
				writeline(output,lout);
			end if;
			X<= (X(6) xor X(7))& X(0 to 6);--Change X and Y in pseudo random order
			Y<= (Y(6) xor Y(7))& Y(0 to 6);
		end loop;
		test_done<='1';
		wait;
	end process;
end a;