ex_3_3_1_get_rate.vhd

来自「This is the course for VHDL programming」· VHDL 代码 · 共 14 行

entity GetRate is
   port(HOUR:in integer;RATE:out real);
end GetRate;
architecture RTL of GetRate is
begin
	process(HOUR)
	begin
		Case HOUR is
			When 0|23 		=> RATE <= 1.00;
			When 20 to 22|1 to 3  =>RATE  <= 1.50;
			When others		=>RATE  <=  2.00;
		End case;
	end process;
end RTL;