ex_p3_17_divider.vhd

This is the course for VHDL programming

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
entity DIVIDER is
   port(A,B : in STD_LOGIC_VECTOR(7 downto 0);
        Q : out  STD_LOGIC_VECTOR(7 downto 0);
        ST_A,ST_B,RST,CLK,START: in STD_LOGIC;
        DONE : out STD_LOGIC);
end DIVIDER;
architecture RTL of DIVIDER is
    signal REG_A,REG_B : STD_LOGIC_VECTOR(7 downto 0);
    signal COUNTER : STD_LOGIC_VECTOR(7 downto 0);
    signal RUN : STD_LOGIC;
begin
    A_PROC:process(RST,CLK,ST_A)
    begin
        if ST_A = '1' then REG_A <= A;
        elsif clk = '1' and clk'event then
            if RUN = '1' then
               REG_A<= REG_A - REG_B;
            end if;
        end if;
    end process A_PROC;
    B_PROC:process(ST_B)
    begin
        if ST_B = '1' then REG_B <= B;
        end if;
    end process B_PROC;
    C_PROC:process(RST,CLK)
    begin
        if RST = '1' then COUNTER <= "00000000";
        elsif clk = '1' and clk'event then
            if RUN = '1' then
                COUNTER <= COUNTER + 1;
            end if;
        end if;
    end process C_PROC;
    RUN_PROC:process(RST,CLK,START)
    begin
        if RST = '1' then RUN <= '0';DONE <= '0';
        elsif clk = '1' and clk'event then
            if START = '1' then
                RUN <= '1';
            end if;
            if REG_A <= REG_B then
                RUN <= '0';DONE <= '1';
            end if;
        end if;
    end process RUN_PROC;
    Q <= COUNTER;
end RTL;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
entity DIVIDER_TB is end DIVIDER_TB;
architecture BEH of DIVIDER_TB is
    signal A,B : STD_LOGIC_VECTOR(7 downto 0);
    signal   Q : STD_LOGIC_VECTOR(7 downto 0);
    signal ST_A,ST_B,RST,CLK,START: STD_LOGIC:='0';
    signal DONE : STD_LOGIC;
begin
    D:entity work.DIVIDER
       port map(A,B,Q,
                ST_A,ST_B,RST,CLK,START,DONE);
    process
    begin
        RST <= '1'; wait for 10 ns;
        RST <= '0'; wait for 10 ns;
        A <= "00011001";
        B <= "00000101";
        ST_A <= '1';ST_B <= '1';
        wait for 10 ns;
        ST_A <= '0';ST_B <= '0';
        wait for 10 ns;
        for i in 1 to 25 loop
           CLK <= '1' ; wait for 50 ns;
           CLK <= '0' ; wait for 50 ns;
       end loop;
       wait;
   end process;
   START <= '1' after 50 ns, '0' after 150 ns;
 end BEH;