ex_3_3_2_mux_4_1.vhd

This is the course for VHDL programming

entity MUX_4_1 is
    port(sel:in bit_vector(1 downto 0);
         I0,I1,I2,I3:in BIT;
         Y :out bit);
end MUX_4_1;
architecture case_arch of MUX_4_1 is
begin
  process(I0,I1,I2,I3,sel)
  begin
   Case SEL is
      When "00" => Y <= I0 ;--after 5 ns;
      When "01" => Y <= I1 ;--after 5 ns;
      When "10" => Y <= I2 ;--after 5 ns;
      When "11" => Y <= I3 ;--after 5 ns;
   End case;
  end process;
end case_arch;