ex_3_5_1_dff.vhd

This is the course for VHDL programming

entity dff is 
	generic(	t_setup:time:= 5 ns;
			t_hold:time := 3 ns;
			t_recovery:time:= 4 ns;
			t_dly_clk_q:time:= 6 ns;
			t_dly_rst_q:time:= 2 ns);
	port (		D,CLK,RST:in BIT:='0';
			Q:out BIT);
	begin
	process(CLK)
	begin
		if  CLK'event and CLK='1' then
				assert d'last_event > t_setup
				report "Setup violation";
		end if;
	end process;
	process(CLK'delayed(t_hold))
	begin
		if  CLK'delayed(t_hold)'event and CLK'delayed(t_hold)='1' then
				assert d'last_event > t_hold
				report "Hold up violation";
		end if;
	end process;
	process(CLK'delayed(t_recovery))
	begin
		if  CLK'delayed'event and CLK'delayed='1' then
				assert (rst = '0')  or   (rst'last_event > t_recovery)
				report "Recovery violation";
		end if;
	end process;
end dff;
architecture a of dff is
begin 
	process(D,CLK,RST)
	begin
		if RST='0' then 
				Q <= '0' after t_dly_rst_q;
		elsif  CLK'event and CLK='1' then
				Q <= D after t_dly_clk_q;
		end if;
	end process;
end a;