ex_2_3_3_sparse_ram.vhd

This is the course for VHDL programming

--Sparse memory using dynamic allocation and linked list
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity SPARSE_RAM is
	port(D :inout  std_logic_vector(7 downto 0);
			A :in     std_logic_vector(31 downto 0);
			RD_BAR,WR_BAR,CS_BAR:in std_logic);
end SPARSE_RAM;
architecture a of SPARSE_RAM is
	type ELEMENT_REC;-- Incomplete type - forward declaration
	type ELEMENT_PTR_T is access ELEMENT_REC;
	type ELEMENT_REC is record
		DATA : std_logic_vector(7 downto 0);
		ADDR : std_logic_vector(31 downto 0);
		NEXT_PTR: ELEMENT_PTR_T;
	end record;
	signal iD : std_logic_vector(7 downto 0);
begin
	PROC:process(RD_BAR,WR_BAR,CS_BAR,iD,D,A)
		variable HEAD_PTR: ELEMENT_PTR_T := NULL;
		variable TEMP_PTR: ELEMENT_PTR_T := NULL;
	begin
		if CS_BAR = '0' and WR_BAR = '0' then --Write operation
			TEMP_PTR := HEAD_PTR;
			loop
			    if TEMP_PTR = NULL then --Reached end but addr not found
			       TEMP_PTR := new ELEMENT_REC;  -- Create a new record
			       TEMP_PTR.DATA := D;
			       TEMP_PTR.ADDR := A;
			       TEMP_PTR.NEXT_PTR := HEAD_PTR;
		                   HEAD_PTR := TEMP_PTR;
			       exit;
			   elsif  TEMP_PTR.ADDR = A then 
TEMP_PTR.DATA := iD;--addr exists
				exit;
			    else 
				TEMP_PTR := TEMP_PTR.NEXT_PTR;-- Keep searching
			    end if;
			end loop;
		elsif CS_BAR = '0' and RD_BAR = '0' then --Read operation
			TEMP_PTR := HEAD_PTR;
			loop
			    if TEMP_PTR = NULL then --Reached end but addr not found
					iD <= "XXXXXXXX"; exit;
			    elsif TEMP_PTR.ADDR = A then 
iD <= TEMP_PTR.DATA;--addr exists
				exit;
			    else 
				TEMP_PTR := TEMP_PTR.NEXT_PTR;-- Keep searching
			    end if;
			end loop;
		end if;
	end process PROC;
	D<= id when RD_BAR = '0' else "ZZZZZZZZ";
	iD<= D when WR_BAR = '0' else "ZZZZZZZZ";
end a;
-- Test bench for Sparse RAM
library IEEE;
use IEEE.std_logic_1164.all;
entity TB_MEM is
end TB_MEM;
architecture a of TB_MEM is
	signal D :std_logic_vector(7 downto 0);
	signal A :std_logic_vector(31 downto 0);
	signal		RD_BAR,WR_BAR,CS_BAR: std_logic;
	component SPARSE_RAM
		port(D :inout  std_logic_vector(7 downto 0);
				A :in     std_logic_vector(31 downto 0);
				RD_BAR,WR_BAR,CS_BAR:in std_logic);
	end component;
	begin
		SRM:SPARSE_RAM port map(D,A,RD_BAR,WR_BAR,CS_BAR);
	process
	begin
		CS_BAR <='0';WR_BAR <= '1';RD_BAR <= '1';
		D <= "00000001";A<=X"0000000f";wait for 10 ns;
		WR_BAR <= '0';wait for 10 ns;WR_BAR <= '1';
		D <= "00000011";A<=X"000000ff";wait for 10 ns;
		WR_BAR <= '0';wait for 10 ns;WR_BAR <= '1';
		D <= "00000111";A<=X"00000fff";wait for 10 ns;
		WR_BAR <= '0';wait for 10 ns;WR_BAR <= '1';
		D <= "00001111";A<=X"0000ffff";wait for 10 ns;
		WR_BAR <= '0';wait for 10 ns;WR_BAR <= '1';
		
		D<="ZZZZZZZZ";A<=X"0000000f";wait for 10 ns;
		RD_BAR <= '0';wait for 10 ns;RD_BAR <= '1';
		A<=X"000000ff";wait for 10 ns;
		RD_BAR <= '0';wait for 10 ns;RD_BAR <= '1';
		A<=X"00000fff";wait for 10 ns;
		RD_BAR <= '0';wait for 10 ns;RD_BAR <= '1';
		A<=X"0000ffff";wait for 10 ns;
		RD_BAR <= '0';wait for 10 ns;RD_BAR <= '1';
		A<=X"000fffff";wait for 10 ns;
		RD_BAR <= '0';wait for 10 ns;RD_BAR <= '1';
		wait for 10 ns;CS_BAR <='1';
		wait;
	end process;
end a;