ex_p2_18_parity_check.vhd

This is the course for VHDL programming

entity PARITY_CHECK is
   port (A: in BIT_VECTOR(4 downto 0); P: out BIT);
end PARITY_CHECK;
architecture A1 of PARITY_CHECK is
begin
   P <= A(0) xor A(1) xor A(2) xor A(3) xor A(4);
end A1;