ex_2_3_3_stack.vhd

来自「This is the course for VHDL programming」· VHDL 代码 · 共 79 行

--Linked list
library IEEE;
use IEEE.std_logic_1164.all;
entity STACK is
	port(DIN :in  std_logic_vector(7 downto 0);
			DOUT:out std_logic_vector(7 downto 0);
			PUSH,POP:in std_logic;
			UFLOW,OFLOW:out std_logic);
end STACK;
architecture a of STACK is
	type ELEMENT_REC;-- Incomplete type - forward declaration
	type ELEMENT_PTR_T is access ELEMENT_REC;
	type ELEMENT_REC is record
		DATA : std_logic_vector(7 downto 0);
		NEXT_PTR: ELEMENT_PTR_T;
	end record;
begin
	process(PUSH,POP,DIN)
		variable HEAD_PTR: ELEMENT_PTR_T := NULL;
		variable TEMP_PTR: ELEMENT_PTR_T := NULL;
		variable COUNT : integer :=0;
	begin
		if PUSH'event and PUSH = '1' then
			if COUNT < 4 then
				COUNT := COUNT + 1;
				TEMP_PTR := new ELEMENT_REC;
				TEMP_PTR.DATA := DIN; 
TEMP_PTR.NEXT_PTR := HEAD_PTR;
				HEAD_PTR := TEMP_PTR;
				OFLOW <= '0';
			else 
				OFLOW <= '1';
				assert false report("Stack Full");
			end if;
		elsif POP'event and POP = '1' then
			if HEAD_PTR /= NULL then
				DOUT <= HEAD_PTR.DATA;
				TEMP_PTR := HEAD_PTR;
				HEAD_PTR := TEMP_PTR.NEXT_PTR;
				deallocate(TEMP_PTR);
				UFLOW <= '0';
			else 
				assert false report("Stack Empty");
				UFLOW <= '1';
			end if;
		end if;
	end process;
end a;
library IEEE;
use IEEE.std_logic_1164.all;
entity TB_STACK is
end TB_STACK;
architecture a of TB_STACK is
	signal 		DIN,DOUT :std_logic_vector(7 downto 0);
	signal		PUSH,POP,UFLOW,OFLOW: std_logic:='0';
	component STACK
		port(DIN :in  std_logic_vector(7 downto 0);
			DOUT:out std_logic_vector(7 downto 0);
			PUSH,POP:in std_logic;
			UFLOW,OFLOW:out std_logic);
	end component;
	begin
		STK:STACK port map(DIN,DOUT,PUSH,POP,UFLOW,OFLOW);
	process
	begin
	    DIN <= "00000001";PUSH <= '1';wait for 10 ns;PUSH <= '0';wait for 10 ns;
	    DIN <= "00000011";PUSH <= '1';wait for 10 ns;PUSH <= '0';wait for 10 ns;
	    DIN <= "00000111";PUSH <= '1';wait for 10 ns;PUSH <= '0';wait for 10 ns;
	    DIN <= "00001111";PUSH <= '1';wait for 10 ns;PUSH <= '0';wait for 10 ns;
	    DIN <= "00011111";PUSH <= '1';wait for 10 ns;PUSH <= '0';wait for 10 ns;
	    POP <= '1';wait for 10 ns;POP <= '0';wait for 10 ns;
	    POP <= '1';wait for 10 ns;POP <= '0';wait for 10 ns;
	    POP <= '1';wait for 10 ns;POP <= '0';wait for 10 ns;		
	    POP <= '1';wait for 10 ns;POP <= '0';wait for 10 ns;
	    POP <= '1';wait for 10 ns;POP <= '0';wait for 10 ns;
	    wait;
	end process;
end a;