ex_p2_16.vhd

This is the course for VHDL programming

entity INV is
   port (A: in BIT; B: out BIT);
end INV;
architecture A1 of INV is
begin
   B <= not A after 10 ns;
end A1;
architecture A2 of INV is
   constant R: real:= 1.5E4;
   constant C: real:= 0.1E-12;
	constant PD:time:= integer(3.0*R*C*1.0E12) *1 ps;
begin
   B <= not A after PD;
end A2;
architecture A3 of INV is
	type CAP is range 1 to 1E9
		units
			ff;
		   pf=1000 ff;
			nf=1000 pf;
			uf=1000 nf;
		end units;
   type RES is range 1 to 1E9
	   units
		   ohms;
		   Kohms=1000 ohms;
		   Mohms=1000 Kohms;
	   End units;
constant R: RES:= 15 Kohms;
constant C: CAP:= 100 ff;
constant PD: time:= (R/ 1 ohms)*(C/1 ff)/1000 *3 ps;
begin
   B <= not A after PD;
 end A3;