de2_1.vhd

This is the course for VHDL programming

Entity TEST is end TEST;
Architecture A of TEST is
	Signal X,Y: BIT;
Begin
		X <= '0', '1' after 80 ns, '0' after 110 ns, '1' after 175 ns;
		Process (X)
		Begin
			Y <= '1', '0' after 40 ns, '1' after 80 ns;
		End process;
End A;