cordic.vhd

This is the course for VHDL programming

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
entity CORDIC_ELEMENT is
	generic(N:integer:=12;--No of bits in register
		  SHIFT:integer:=0);--Shift count for this stage
	port(x_in,y_in:in std_logic_vector(N-1 downto 0);
			z_in:in std_logic_vector(N-1 downto 0);
			const 	:in std_logic_vector(N-1 downto 0);
			x_out,y_out:out std_logic_vector(N-1 downto 0);
			z_out: out std_logic_vector(N-1 downto 0);
			di:in std_logic;
			do:out std_logic
			);
end CORDIC_ELEMENT;
architecture RTL of CORDIC_ELEMENT is
	signal z:std_logic_vector(N-1 downto 0);
	function SH_RA(slv: std_logic_vector) 
			return std_logic_vector is
	begin
		return To_stdlogicvector(To_bitvector(slv) sra SHIFT);   
	end SH_RA;
begin
	z     <=  z_in - const when di = '0' else
					z_in + const;
	x_out <= x_in - SH_RA(y_in) when di = '0' else
				  x_in + SH_RA(y_in);
	y_out <= y_in + SH_RA(x_in) when di = '0' else
				  y_in - SH_RA(x_in);
	do <= z(N-1);--Sign bit of angle
	z_out <= z;
end RTL;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_arith.all;
entity CORDIC is
	generic(N:integer:=12;--No of bits in registers
		M:integer:=12 --No of iteration stages
		);
	port(z_in:in std_logic_vector(N-1 downto 0);
		x_out,y_out:out std_logic_vector(N-1 downto 0)
		);
end CORDIC;
architecture RTL of CORDIC is
	type sig_array is array (0 to M) of std_logic_vector(N-1 downto 0);
	type con_array is array (0 to M) of std_logic_vector(N-1 downto 0);
	signal x,y,z:sig_array;
	signal const:con_array
		  :=(
			CONV_STD_LOGIC_VECTOR(450,M),
			CONV_STD_LOGIC_VECTOR(265,M),
			CONV_STD_LOGIC_VECTOR(140,M),
			CONV_STD_LOGIC_VECTOR(71,M),
			CONV_STD_LOGIC_VECTOR(35,M),
			CONV_STD_LOGIC_VECTOR(18,M),
			CONV_STD_LOGIC_VECTOR(9,M),
			CONV_STD_LOGIC_VECTOR(4,M),
			CONV_STD_LOGIC_VECTOR(2,M),
			CONV_STD_LOGIC_VECTOR(1,M),
			CONV_STD_LOGIC_VECTOR(1,M),
			CONV_STD_LOGIC_VECTOR(0,M),
			others => (others=>'0')
		      );
	signal d:std_logic_vector(M downto 0);
	constant zero: std_logic_vector(N-1 downto 0):= CONV_STD_LOGIC_VECTOR(0,N);
	constant x_init:std_logic_vector(N-1 downto 0):= CONV_STD_LOGIC_VECTOR(607,N);
begin
	x(0) <= x_init;
	y(0) <= zero;
	z(0) <=z_in;
	x_out <= x(M);
	y_out <= y(M);
	d(0) <= '0';
	gen:for i in 0 to M-1 generate
		CE:entity work.CORDIC_ELEMENT
				generic map(N,i)
				port map(x(i),y(i),z(i),const(i),
					   x(i+1),y(i+1),z(i+1),d(i),d(i+1));
				end generate;
end RTL;