fir.vhd

This is the course for VHDL programming

--             LINEAR PHASE FIR FILTER
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
package filt is
    type const_array is array(positive range <>)OF SIGNED(7 downto 0);
end package;
use work.filt.all;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_textio.ALL;
use std.textio.all;
ENTITY FIRFILT8 IS
	generic(con:const_array:=("00110110","00110001","00100011","00010000"));
	--generic(con:const_array:=(54,49,35,16));
	PORT( X:IN  SIGNED( 7 DOWNTO 0);
		Y:OUT SIGNED(15 DOWNTO 0);
		CLK,RST:IN STD_LOGIC
	    );

END FIRFILT8;
ARCHITECTURE RTL OF FIRFILT8 IS
	TYPE X_ARRAY IS ARRAY(1 TO 2*con'high-2) OF SIGNED( 7 DOWNTO 0);
	SIGNAL XA:X_ARRAY;--FIR SHIFT REGISTER
BEGIN
	SHIFT_PROC:PROCESS(CLK,RST,XA,X)
	BEGIN
		IF RST = '1' THEN XA <= (OTHERS => "00000000");
		ELSIF CLK'EVENT AND CLK = '1' THEN
			XA(1) <= X;
			FOR I IN 1 TO XA'HIGH-1 LOOP
				XA(I+1) <= XA(I);--SHIFT CONTENTS OF X ARRAY
			END LOOP;
		END IF;
	END PROCESS SHIFT_PROC;
	
	SUM_PROC:PROCESS(XA,X)
		variable sum :SIGNED(18 downto 0);
		variable sum1:SIGNED( 8 downto 0);
		variable sum2:SIGNED( 8 downto 0);
	BEGIN
		--X IS NOT PART OF X ARRAY, HENCE HANDLED SEPARATELY
		sum1:= (X(7) & X) + XA(XA'HIGH);
		sum:= (sum1(8)&sum1(8)&sum1) * con(con'high);
		sum:= sum + XA(con'high-1)*con(1);--Center element
		
		FOR I IN 1 to (con'high-2) LOOP
			sum2:= (XA(con'high-1-I)(7) &  XA(con'high-1-I))
+XA(con'high-1+I);
		   	sum := sum+ sum2 * con(I+1);
		END LOOP;
		Y <= sum(15 downto 0);
	END PROCESS SUM_PROC;
	
END RTL;