cross_bar.vhd

This is the course for VHDL programming

library ieee;
use ieee.std_logic_1164.all;
entity BUS_ARB is
	port ( REQ1,REQ2,REQ3,CLK,RST:in STD_LOGIC;GRANT1,GRANT2,GRANT3:out STD_LOGIC);
end BUS_ARB;
architecture BEH of BUS_ARB is
	type STATE_TABLE is(IDLE,G1,G2,G3);
	signal STATE,N_STATE:STATE_TABLE;
begin
	STATE_PROC:process(REQ1,REQ2,REQ3,CLK,RST)
	begin
		if  RST = '1' then STATE<= IDLE;
		elsif CLK'event and CLK = '1' then STATE<=N_STATE;
		end if;
	end process STATE_PROC;
	N_STATE<= G1 when (state=idle and REQ1='1')else
		          G1 when (state=  G1 and REQ1='1')else
		       G1 when (state=  G2 and REQ1='1' and REQ2='0') else
		       G1 when (state=  G3 and REQ1='1' and REQ3='0') else
		       G2 when (state=idle and REQ2='1' and REQ1='0') else
		       G2 when (state=  G1 and REQ2='1' and REQ1='0') else
		       G2 when (state=  G2 and REQ2='1')else
		       G2 when (state=  G3 and REQ2='1' and REQ1='0' and REQ3='0') else
		       G3 when (state=idle and REQ3='1' and REQ1='0' and REQ2='0') else
		       G3 when (state=  G1 and REQ3='1' and REQ1='0' and REQ2='0') else
		       G3 when (state=  G2 and REQ3='1' and REQ1='0' and REQ2='0') else
		       G3 when (state=  G3 and REQ3='1')else
		      IDLE;
	GRANT1<= '1' when STATE = G1 else '0';
	GRANT2<= '1' when STATE = G2 else '0';
	GRANT3<= '1' when STATE = G3 else '0';

end BEH;
library ieee;
use ieee.std_logic_1164.all;
entity CROSSBAR is
	port ( 	data1,data2,data3:in std_logic_vector(7 downto 0);
		dout1,dout2,dout3:out std_logic_vector(7 downto 0);
		dest1,dest2,dest3:in std_logic_vector(7 downto 0);
		req1,req2,req3,CLK,RST:in std_logic;
		gr1,gr2,gr3:out std_logic
	       );
end CROSSBAR;
architecture STRUCT of CROSSBAR is
	signal R1,R2,R3,G1,G2,G3:std_logic_vector(3 downto 1);
	component BUS_ARB 
	   	port (REQ1,REQ2,REQ3,CLK,RST:in STD_LOGIC;
			GRANT1,GRANT2,GRANT3:out STD_LOGIC);
	end component;
begin
	GENBA:for i in 1 to 3 generate
	     GBA:BUS_ARB port map(R1(i),R2(i),R3(i),CLK,RST,G1(i),G2(i),G3(i));
	end generate;
	R1(1)<= '1' when req1='1' and dest1(1)='0' and dest1(0)='0' else '0';
	R1(2)<= '1' when req1='1' and dest1(1)='0' and dest1(0)='1' else '0';
	R1(3)<= '1' when req1='1' and dest1(1)='1' and dest1(0)='0' else '0';

	R2(1)<= '1' when req2='1' and dest2(1)='0' and dest2(0)='0' else '0';
	R2(2)<= '1' when req2='1' and dest2(1)='0' and dest2(0)='1' else '0';
	R2(3)<= '1' when req2='1' and dest2(1)='1' and dest2(0)='0' else '0';

	R3(1)<= '1' when req3='1' and dest3(1)='0' and dest3(0)='0' else '0';
	R3(2)<= '1' when req3='1' and dest3(1)='0' and dest3(0)='1' else '0';
	R3(3)<= '1' when req3='1' and dest3(1)='1' and dest3(0)='0' else '0';
	dout1<=data1 when G1(1) = '1' else "ZZZZZZZZ";
	dout1<=data2 when G2(1) = '1' else "ZZZZZZZZ";
	dout1<=data3 when G3(1) = '1' else "ZZZZZZZZ";
	dout2<=data1 when G1(2) = '1' else "ZZZZZZZZ";
	dout2<=data2 when G2(2) = '1' else "ZZZZZZZZ";
	dout2<=data3 when G3(2) = '1' else "ZZZZZZZZ";
	dout3<=data1 when G1(3) = '1' else "ZZZZZZZZ";
	dout3<=data2 when G2(3) = '1' else "ZZZZZZZZ";
	dout3<=data3 when G3(3) = '1' else "ZZZZZZZZ";
	gr1<=G1(1) or G1(2) or G1(3);
	gr2<=G2(1) or G2(2) or G2(3);
	gr3<=G3(1) or G3(2) or G3(3);
end STRUCT;