rca_4bit.vhd

This is 8bit multiplier VHDL code. It s consist of full adder, ripple carry adder(4bit, 8bit) multip

library IEEE;                                                            
use IEEE.STD_LOGIC_1164.ALL;                                             
use IEEE.STD_LOGIC_ARITH.ALL;                                            
use IEEE.STD_LOGIC_UNSIGNED.ALL;                                         
                                                                         
                               
                                                                         
entity RCA_4bit is                                                       
 Port ( a, b : in std_logic_vector(3 downto 0);                          
      c : in std_logic;                                                  
    sum :  out std_logic_vector(3 downto 0);                             
    carry_out : out std_logic);                                          
 end RCA_4bit;                                                           
                                                                         
architecture Behavioral of RCA_4bit is                                   
                                                                         
component full_adder                                                     
 Port (a, b, c : in std_logic;                                           
    sum, carry_out : out std_logic );                                    
end component;                                                           
                                                                         
signal tmp_cin : std_logic_vector(2 downto 0);                           
                                                                         
begin                                                                    
                                                                         
U0 : full_adder port                                                     
map(a=>a(0), b=>b(0), c=>c, sum=>sum(0), carry_out=>tmp_cin(0));         
                                                                         
U1 : full_adder port                                                     
map(a=>a(1), b=>b(1), c=>tmp_cin(0), sum=>sum(1), carry_out=>tmp_cin(1));
                                                                         
U2 : full_adder port                                                     
map(a=>a(2), b=>b(2), c=>tmp_cin(1), sum=>sum(2), carry_out=>tmp_cin(2));
                                                                         
U3 : full_adder port                                                     
map(a=>a(3), b=>b(3), c=>tmp_cin(2), sum=>sum(3), carry_out=>carry_out); 
                                                                         
end Behavioral;