multiplier_8_bit_tb.vhd

来自「This is 8bit multiplier VHDL code. It s 」· VHDL 代码 · 共 105 行

--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY multiplier_8_bit_tb IS
END multiplier_8_bit_tb;

ARCHITECTURE behavior OF multiplier_8_bit_tb IS 

	COMPONENT multiplier_8_bit
	PORT(
		rst	: in std_logic;
		clk	  : in std_logic;

		A : in std_logic_vector(7 downto 0);
		B : in std_logic_vector(7 downto 0);		

		M  : out std_logic_vector(15 downto 0)	  		              
		                      		
		);                                              		
	END COMPONENT;
	
	
 
	signal rst :  std_logic;
	signal clk   :  std_logic;
  signal A :	std_logic_vector(7 downto 0);
	signal B :  std_logic_vector(7 downto 0);
	      
 	signal M  :  std_logic_vector(15 downto 0);
 
	----------------------------------------
 constant clkfreq_mhz		: integer := 33;
 constant clk_period		: time := 1 us/clkfreq_mhz; 
 signal sim_done			: std_logic;

BEGIN
   process		--clock generation with 50% duty cycle
   begin
      U_clk : while sim_done /= '1' loop
         clk                       <= '0'; wait for (clk_period * 0.5);
         clk                       <= '1'; wait for (clk_period * 0.5);
      end loop U_clk;
      wait;
   end process;
   
	uut: multiplier_8_bit PORT MAP(
		rst => rst,                                    
		clk   => clk,                                        
		   
    A => A,
    B => B,


    M  => M                                                       
	);                                                    	
                                                        
                                                        
                                                  

   tb : process
  
   	  
   begin  

    sim_done 				<= '0';                                             
   
    rst   <= '0';  
    A   <= "00000000"; 
    B   <= "00000000";     
    wait for (clk_period * 5);
 --------------------------------------   
    rst		<= '1'; 
    A   <= "00000001";  
    B   <= "10000000";  
    wait for (clk_period * 1);
    rst		<= '0'; 	
    wait for (clk_period * 16);	
----------------------------------------
    rst		<= '1'; 
    A   <= "00001110";  
    B   <= "00110000";  
    wait for (clk_period * 1);
		rst		<= '0'; 	           
    wait for (clk_period * 16);	 

----------------------------------------
    rst		<= '1'; 
    A   <= "00001110";  
    B   <= "11111111";  
    wait for (clk_period * 1);
		rst		<= '0'; 	           
    wait for (clk_period * 16);	   
   
   sim_done 				<= '1';
   
   end process;
-- *** End Test Bench - User Defined Section ***

END;