full_adder.vhd

来自「This is 8bit multiplier VHDL code. It s 」· VHDL 代码 · 共 23 行

library IEEE;                                                            
use IEEE.STD_LOGIC_1164.ALL;                                             
use IEEE.STD_LOGIC_ARITH.ALL;                                            
use IEEE.STD_LOGIC_UNSIGNED.ALL;                                         
                                                                         
                                  
                                                                         
entity full_adder is                                                     
Port (a, b, c : in std_logic;                                            
  sum, carry_out : out std_logic);                                       
end full_adder;                                                          
                                                                         
architecture Behavioral of full_adder is                                 
                                                                         
begin                                                                    
sum <= a xor b xor c;                                                    
carry_out <= (a and b) or (b and c) or (c and a);                        
                                                                         
end Behavioral;