rca_8bit.vhd

来自「This is 8bit multiplier VHDL code. It s 」· VHDL 代码 · 共 35 行

library IEEE;                                                            
use IEEE.STD_LOGIC_1164.ALL;                                             
use IEEE.STD_LOGIC_ARITH.ALL;                                            
use IEEE.STD_LOGIC_UNSIGNED.ALL;                                         
                                                                         
                                   
                                                                         
entity RCA_8bit is                                                       
Port ( a, b : in std_logic_vector(7 downto 0);                           
      c : in std_logic;                                                  
    sum :  out std_logic_vector(7 downto 0);                             
    carry_out : out std_logic);                                          
end RCA_8bit;                                                            
                                                                         
architecture Behavioral of RCA_8bit is                                   
                                                                         
component RCA_4bit                                                       
Port ( a, b : in std_logic_vector(3 downto 0);                           
      c : in std_logic;                                                  
    sum :  out std_logic_vector(3 downto 0);                             
    carry_out : out std_logic);                                          
end component;                                                           
                                                                         
signal temp_cin : std_logic;                                             
                                                                         
begin                                                                                                                                                                             

U0 : RCA_4bit port                                                       
map (a => a(3 downto 0), b => b(3 downto 0), c => c, sum => sum(3 downto 0),carry_out=>temp_cin);
                                                                                                                  
U1 : RCA_4bit port                                                       
map (a => a(7 downto 4), b => b(7 downto 4), c=>temp_cin, sum => sum(7 downto 4), carry_out=>carry_out);                                                                               
                                                                         
end Behavioral;